От: SoC-NewsAlert@design-reuse.com
Отправлено: 15 июня 2004 г. 12:45
Кому: Michael Dolinsky
Тема: D&R SoC News Alert - June 15, 2004
DR SoC News Alert
Design And ReuseDesign And ReuseDesign And Reuse
EETimes Network
June 15, 2004    


Welcome to issue of June 15, 2004 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

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Quad 1 to 4.25Gbps SerDes PHY for FC/GE/SATA/SAS from TaraCom Integrated Products
1.056GHz programmable clock-multiplying PLL from ChipIdea Microelectronics
I2C Verification IP (eVC) from HDL Design House
PCI Express PHY from TriCN, Inc.
DesignWare AMBA AXI Verification IP from Synopsys
SMIC 0.18um USB 2.0 Transceiver Macrocell Interface (UTMI) PHY from Verisilicon, Inc.
Wanted IPs :
  • FM receiver - digital architecture
  • PCI 33MHz 0.25um Technology IO Only
    • Techniques for verifying multiprocessor designs
    Meeting the Challenges of VoIP ATA Designs
    Developing an ATE strategy for PCI Express
    Transition to 90-nm raising tough design issues
    IP Market to Grow 22%
    EETimes' Industry Challenge: When requirements outrun an architecture
    EETimes' Industry Challenge: Assessing the structured-ASIC alternative
    IP/SOC PRODUCTS
    OCP-IP Highlights Texas Instruments Use of OCP in Leading-edge OMAP 2 Architecture
    MIPS Technologies Introduces The MIPS Consumer Audio Platform, The Industry's Most Comprehensive Audio Solution
    Fraunhofer IIS audio codecs integrated in MIPS Consumer Audio Platform
    LSI Logic Demonstrates 12 Gbit/S Serial Interface Circuitry in 90 Nanometer Process Technology
    Avery Design and GDA Technologies Introduce MaxCov for PCI Express Compliance Verification
    Ericsson Paves Way For Bluetooth Stereo Headsets
    True Circuits Introduces New Line of Phase-Locked Loop Hard Macros; Significantly Smaller PLL Sizes Achieved Without Sacrificing Performance
    Sarnoff TakeCharge Design Approach Delivers Chip I/O Size Reduction for Altera FPGAs
    TriCN and Tallika Announce Collaboration on Interoperable Full PCI Express Solution
    TriCN Partners With Cascade For Full PCI-Express Solution
    Cavendish Kinetics announces a major new embedded memory technology
    Jeda Technologies Announces PCI-X, SPI-4, Ethernet, ARM AMBA Verification IP at DAC
    STRUCTURED ASIC
    Flextronics Semiconductor partners with Magma and eASIC on comprehensive and affordable Structured ASIC Solutuion
    FOUNDRIES
    SOI mobility harmed by scattering, Toshiba researchers report
    XILINX and UMC Develop Industry's First FPGAs to Utilize Triple-Oxide 90nm Technology
    TSMC's Fab 6 Production Exceeds 70,000 8-inch Wafers per Month
    TSMC May Sales Set Record High
    IBM introduces advanced design methodology to increase performance and reduce power consumption in custom chips
    BUSINESS
    SuperH to close, engineers reassigned, says report
    eInfochips expands market reach in North America and Asia, reinforces engineering team strength
    Avery Design and GDA Technologies Expand Partnership to Advanced Switching
    QualCore Logic Named Member of IBM IP Collaboration Program Provides Crucial Semiconductor Intellectual Property to Mutual Customers
    GET and ARC International Sign Distribution Agreement
    FINANCIAL RESULTS
    Faraday Announces Revenue for May Record Revenue of NT$ 420 Million
    DEALS
    Synopsys DesignWare IP Core for PCI Express Powers Realtek Single-Chip Gigabit Ethernet Solution
    SRS TruSurround XT Chosen by MIPS Technologies as Standard Virtual Surround Sound Technology for Consumer Audio Platform
    DESIGN SERVICES
    Accent Launches "Highway to Silicon"
    EMBEDDED SYSTEMS
    Toshiba to start production of industry's first SoC with the X architecture
    FPGA/CPLD
    Actel's Libero IDE Delivers Industry's Best Mix of Design Tools, Superior Functionality and Ease-of-Use
    Altera Collaborates with Synopsys on HardCopy Structured ASICs
    EDA
    NEC engineers advance hardware/software co-verification
    SPIRIT Consortium drives IP re-use and interoperability with release of specification
    Avertec and Dolphin Integration announce partnership in Design Check Innovation

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    - Panel on IP Quality & Verification (brought to you by Verisity)
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